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verilog中的相等

上一篇 / 下一篇  2018-08-29 00:45:46 / 个人分类:Verilog

==/!= Vs ===/!==
  • Logic equality: ==
    • “a==b”
      • Only compare when a or b is 0 or 1
      • If a or b is “x”, “z”, result is always “x”/false
      • tests for 1 and 0, all other will result in x
  • Case equality: ===
    • “a===b”
      • Will compare 0/1/x/z
      • When both are x or both are z, result is 1
      • tests for 1, 0, z and x
      • never resulting in X
Wildcard Equality: ==?, !=?
  • Make few bits in RHS as don't-cares
  • a =?= b 
  • a equals b, X and Z values act as wild cards
  • may result in X if the left operand contains an x or Z



TAG: case equality Logic logic verilog Verilog

 

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